On ladder diagrams compilation and synthesis to FPGA implemented reconfigurable logic controller

The paper presents synthesis process of a hardware implemented reconfigurable logic controller from a ladder diagram according to IEC61131-3 requirements. It is focused on the originally developed a high-performance LD processing method. It is able to process a set of diagrams restricted to logic operations in a single clock cycle independently from the number of processed rungs. The paper considers the compilation of the ladder diagram into an intermediate form suitable for logic synthesis process according to developed processing method. The enhanced data flow graph (EDFG) has been developed for the intermediate representation of an LD program. The original construction of the EDFG with attributed edges has been described. It allows for efficient representation and processing of logic and arithmetic formulas. The set of compilation algorithms that allow to preserve serial analysis order and to obtain massively parallel processing unit are presented. The overview of a hardware mapping concludes the presented considerations

Shared-Semaphored Cache Implementation for Parallel Program Execution in Multi-Core Systems

The paper brings forward the idea of multi-threadedcomputation synchronization based on the shared semaphoredcache in the multi-core CPUs. It is dedicated to the implementationof multi-core PLC control, embedded solution or parallelcomputation of models described using hardware description languages.The shared semaphored cache is implemented as guardedmemory cells within a dedicated section of the cache memory thatis shared by multiple cores. This enables the cores to speed up thedata exchange and seamlessly synchronize the computation. Theidea has been verified by creating a multi-core system model usingVerilog HDL. The simulation of task synchronization methodsallows for proving the benefits of shared semaphored memorycells over standard synchronization methods. The proposed ideaenhances the computation in the algorithms that consist ofrelatively short tasks that can be processed in parallel andrequires fast synchronization mechanisms to avoid data raceconditions

Shared-Semaphored Cache Implementation for Parallel Program Execution in Multi-Core Systems

The paper brings forward an idea of multi-threaded computation synchronization based on the shared semaphored cache in the multi-core CPUs. It is dedicated to the implementation of multi-core PLC control, embedded solution or parallel computation of models described using hardware description languages. The shared semaphored cache is implemented as guarded memory cells within a dedicated section of the cache memory that is shared by multiple cores. This enables the cores to speed up the data exchange and seamlessly synchronize the computation. The idea has been verified by creating a multi-core system model using Verilog HDL. The simulation of task synchronization methods allows for proving the benefits of shared semaphored memory cells over standard synchronization methods. The proposed idea enhances the computation in the algorithms that consist of relatively short tasks that can be processed in parallel and requires fast synchronization mechanisms to avoid data race conditions

Design and synthesis of new quinazolin-4-one derivatives with negative mGlu7mGlu_7 receptor modulation activity and antipsychotic-like properties

Following the glutamatergic theory of schizophrenia and based on our previous study regarding the antipsychotic-like activity of mGlu7 NAMs, we synthesized a new compound library containing 103 members, which were examined for NAM mGlu7 activity in the T-REx 293 cell line expressing a recombinant human mGlu7 receptor. Out of the twenty-two scaffolds examined, active compounds were found only within the quinazolinone chemotype. 2-(2-Chlorophenyl)-6-(2,3-dimethoxyphenyl)-3-methylquinazolin-4(3H)-one (A9-7, ALX-171, mGlu7 IC50 = 6.14 µM) was selective over other group III mGlu receptors (mGlu4 and mGlu8), exhibited satisfactory drug-like properties in preliminary DMPK profiling, and was further tested in animal models of antipsychotic-like activity, assessing the positive, negative, and cognitive symptoms. ALX-171 reversed DOI-induced head twitches and MK-801-induced disruptions of social interactions or cognition in the novel object recognition test and spatial delayed alternation test. On the other hand, the efficacy of the compound was not observed in the MK-801-induced hyperactivity test or prepulse inhibition. In summary, the observed antipsychotic activity profile of ALX-171 justifies the further development of the group of quinazolin-4-one derivatives in the search for a new drug candidate for schizophrenia treatment

A Mixed Hardware-Software Implementation of a High-Performance PMSM Controller

Implementation of the permanent magnet synchronous motor vector control implies strong time dependencies. The control process requires precise measurement of motor shaft position and winding currents to establish correct driving. The tight time dependencies are difficult to achieve using a programmatic approach. Specific controller architecture is proposed for programmable systems on chip architectures enabling operations precise timing and improved processing performance. The controller is decomposed into a dedicated hardware interface system and programmatic part for easy implementation and modification of the control algorithm. The proposed architecture offers precise and repeatable input-output operations timing and assures meeting tight time dependencies. The control algorithm is executed as an interrupt service requested by the interface system in a constant processing period with relatively weak time dependencies. Additionally, the interface system preprocesses input and output signals reducing the computation effort and saving time for algorithm computations. The specific implementation enabled improved measurement of the motor’s windings current with suppression of disturbances caused by inverter operation. There is shown an efficient implementation of Parke’s and Clarke’s transformations using specific resources of modern programmable logic devices. In opposite to the software-managed implementation presented implementation assures completing processing faster, using a minimal number of hardware resources of the FPGA platform and offering the highest flexibility of software part implementation

Reconfigurable Logic Controller—Direct FPGA Synthesis Approach

Programmable logic controllers are commonly used in automation systems. Continuously growing demands result in the growth of control program complexity. The classic approach, based on programmatic serial-cyclic execution, results in an unacceptable extension of response time. To overcome long response time massive parallel program execution is proposed. It utilize direct in hardware program implementation in field programmable devices. The paper brings a formal method of representing control programs using flow graphs and enabling single cycle computations. The developed method accepts ladder diagrams (LD) and sequential function charts (SFC), according to IEC61131-3 standard requirements. It is capable of handling logic and arithmetic computations, enabling its hardware mapping. The intermediate form is optimized using flow graph representation and BDDs for analyzing logic dependencies. The BDD representation of logic dependencies enables direct mapping to lookup tables of a selected FPGA family. All the above steps deliver high-performance and direct hardware implementation of the control program given by standard languages. The controller response time is short, predictable, and independent from logic conditions during program execution